1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof with a static random access memory (SRAM) mounted thereon.
2. Description of the Related Art
In recent years, influence of cosmic rays such as a rays and neutron rays on a semiconductor device has been highlighted as miniaturization of the semiconductor device. This includes the fact that an occurrence of a soft error phenomenon to be a false operation of a device caused by generating pairs of electrons and holes in a semiconductor substrate and becoming a current to flow into an electrode when the cosmic rays are incident to the semiconductor substrate with an element formed thereon.
For instance, in a semiconductor element shown in FIG. 1, when an a ray 120 with high energy is incident to a semiconductor substrate 101, the semiconductor element generates pairs of electrons and holes 121 in the semiconductor substrate along with an incident locus. The generated electric charges flow out as a current depending on an electric potential distribution in the semiconductor substrate. Here, a diffusion layer n+ isolated by element isolating dielectric films 108 having been biased to a power supply voltage Vdd and a P-well region 102 of a substrate part having been biased to a ground voltage GND, the generated electrons and holes flow into the diffusion layer n+ 105 and the P-well region 102, respectively.
In a dynamic random access memory (DRAM) one memory cell is comprised of one MOSFET and one capacitor storing data as electric charges therein; however the DRAM poses a problem such that an electric charge quantity of the capacitor is easily varied due to the electric charges generated from the cosmic rays in the manner described above. Therefore, a method has been used, in which the structure of the DRAM is varied from a planer capacitor into a deep trench capacitor forming an electrode on the inner wall of a deep trench formed in a substrate so as to maintain a capacity of the capacitor as well as improve a soft error resistance.
In contrast, in the SRAM, a bit cell is comprised of a P-channel MOSFET and an N-channel MOSFET combining alternatively. For example, as a cross-sectional view and an top view are shown in FIG. 2 and FIG. 3, respectively, in an N-well 102a and a P-well 102b formed in the p-semiconductor substrate 101, a P-channel MOSFET 107a and an N-channel MOSFET 107b are comprised of gate electrodes 104a and 104b, respectively, and high-density diffusion layers 105 and low-density diffusion layers 106′ formed so as to sandwich the directly under part of the gate electrodes 104a and 104b, respectively. These P-channel and N-channel MOSFETs 107a and 107b are isolated by the element isolating dielectric films 108 and connected to metal wirings 110 such as word lines, bit lines and Vdds, respectively.
As a circuit diagram of an SRAM cell structured as mentioned above and shown in FIG. 4, the SRAM cell is biased even in storing data and the data is stored owing to balance of a voltage applied to a MOSFET circuit, so that the influence caused by the cosmic rays has not posed a large problem. As the semiconductor device becomes minute, however, the inner capacity of the SRAM, etc., becomes small to about 1 fF and a breakdown of stored data due to a soft error becomes no longer allowed to be neglected.
Up to this day, to improve the soft error resistance, a variety of methods have been disclosed in, for instance, JP 7-183400. However, a plurality of electric charges generated from the cosmic rays incident into a substrate; disturb data-storing currents of a plurality of bit cells. So that even with a data correction conducted in a circuit, the method has posed a problem that it is hard to conduct accurate data-storing.